Bounding the severity of hysteretic transient effects in partially-depleted SOI CMOS

Hysteretic time-transient floating-body effects are of great concern in designing partially-depleted (PD) SOI circuits. It has been demonstrated that these hysteretic floating-body effects can give rise to irregular signal propagation such as frequency dependent propagation and pulse stretching. However, these floating-body effects are known to offer enhancement of current drive over an equivalent SOI body-contacted device. Thus, it may be desirable to keep the body floating so long as the hysteretic effects can be minimized by proper device design. In order to evaluate a device design for hysteresis effect, a methodology is required which can bound the severity of hysteretic effects. In this work, a simulation method using MEDICI to evaluate PD-SOI MOSFET hysteresis effects is introduced and applied to several device designs. Two designs which eliminate hysteretic floating-body effects in PD-SOI CMOS inverters are demonstrated