Approaching the 35 nm technology node: technical requirements and key challenges in front-end processing

Author

Cleavelin, Rinn

Author_Institution

Front End Processes Div., SEMATECH, USA

fYear

1999

fDate

1999

Firstpage

338

Abstract

Summary form only given. The 1999 International Technology Roadmap for Semiconductors (ITRS) is currently being developed and is scheduled for release in November 1999. Key to this roadmap is the evolutionary development of manufacturable front-end processes that will help the industry maintain the historical product performance trend. This talk will focus on the key challenges, technology requirements and potential solutions as presented in the roadmap in the Front-End Process (FEP) areas of starting materials, surface preparation, etch, doping, thermal/thin films and device modeling, The talk will also explore the FEP grand challenge: a CMOS compatible, robust, high-K dielectric gate stack process

Keywords

CMOS integrated circuits; etching; integrated circuit manufacture; nanotechnology; product development; semiconductor doping; semiconductor process modelling; technological forecasting; 1999 International Technology Roadmap for Semiconductors; 35 nm; CMOS compatible robust process; device modeling; doping; etch; front-end processing; high-K dielectric gate stack process; key challenges; product performance; surface preparation; technical requirements; thermal/thin films; CMOS technology; Dielectric thin films; Doping; Etching; High K dielectric materials; Job shop scheduling; Manufacturing industries; Manufacturing processes; Semiconductor device manufacture; Thin film devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI

Conference_Location

Boston, MA

ISSN

1078-8743

Print_ISBN

0-7803-5217-3

Type

conf

DOI

10.1109/ASMC.1999.798260

Filename

798260