Title :
A 8-bit parity code generator based on multigate single electron transistor
Author :
Wu, Gang ; Cai, Li ; Kang, Qiang ; Wang, Sen ; Li, Qin
Author_Institution :
Sci. Inst., Air Force Eng. Univ., Xian
Abstract :
This paper present a circuit design of a 8-bit parity code generator using single-electron transistors (SETs). The design is based on the characteristic of multigate single-electron transistor and a single-electron transistor can realize a n-input exclusive-OR (XOR) gate or XNOR gate. The proposed design enable us to construct a 8-bit parity code generator using only four SETs. The simulation is performed with the circuit simulator PSpice, where the MIB model.
Keywords :
SPICE; logic gates; parity check codes; single electron transistors; 8-bit parity code generator; MIB model; PSpice; XNOR gate; circuit simulator; multigate single electron transistor; n-input exclusive-OR gate; CMOS technology; Capacitance; Circuit simulation; Circuit synthesis; Design engineering; Integrated circuit technology; Logic devices; Single electron transistors; Tunneling; Voltage; Parity code generator; XNOR gate; XOR gate; multigate single-electron transistor;
Conference_Titel :
Nano/Micro Engineered and Molecular Systems, 2008. NEMS 2008. 3rd IEEE International Conference on
Conference_Location :
Sanya
Print_ISBN :
978-1-4244-1907-4
Electronic_ISBN :
978-1-4244-1908-1
DOI :
10.1109/NEMS.2008.4484314
