DocumentCode :
3232997
Title :
Highly optimized intra prediction architecture for high resolution application
Author :
Choi, Jinha ; Yu, Jeyun ; Kim, Jaeseok
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
fYear :
2010
fDate :
6-9 Dec. 2010
Firstpage :
390
Lastpage :
393
Abstract :
This paper proposes a new intra prediction architecture for high resolution applications. The standard intra prediction has a data dependency for the pipelined processing. To enable the pipelined intra prediction architecture, processing order changing methods and additional processing schedulers are proposed. However, previous methods are not considered for the parallel processing which is a key issue of high resolution applications, such as High Definition videos or Ultra High Definition videos. The proposed intra prediction architecture has a new scheduler and two difference calculation processing units for the high performance parallel processing in intra 4×4 luminance prediction and intra 8x8 luminance prediction. The proposed architecture reduces processing time by about 43.40% compared with the standard and by about 20.10% compared with previous architecture.
Keywords :
high definition video; parallel processing; pipeline processing; video coding; H.264/AVC; data dependency; high resolution application; luminance prediction; order changing methods; parallel processing; pipelined intra prediction architecture; pipelined processing; processing schedulers; ultra high definition videos; Computer architecture; Discrete cosine transforms; Encoding; Hardware; Mathematical model; Parallel processing; Pixel; H.264/AVC; Hardware Architecture; Intra Prediction; Parallel Processing; Video Codec;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
Type :
conf
DOI :
10.1109/APCCAS.2010.5775074
Filename :
5775074
Link To Document :
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