A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays

General purpose processors (GPPs) and ASICs have traditionally been the common means for building and implementing artificial neural networks (ANNs). However such computing paradigms suffer from the constant need of establishing a trade-off between flexibility and performance. Due to the technological advance in the development of programmable logic devices, field programmable gate arrays (FPGAs) have become attractive for realizing ANNs. FPGAs have shown to exhibit excellent flexibility in terms of reprogramming the same hardware and at the same time achieving good performance by enabling parallel computation. In this paper various implementations of ANNs on FPGAs are investigated and compared. The research described in this paper proposes three partially parallel architectures and a fully parallel architecture to realize the back-propagation algorithm on an FPGA. The proposed designs are coded in Handel-C and functionally verified by synthesizing them on a Virtex2000e FPGA chip. The partially parallel architectures and the fully parallel architecture are found to be 2.25 and 4 times faster than the software implementation respectively for different benchmarks.