• DocumentCode
    3233159
  • Title

    On the design of two-level reconfigurable architectures

  • Author

    Lange, Sebastian ; Middendorf, Martin

  • Author_Institution
    Dept. of Comput. Sci., Leipzig Univ.
  • fYear
    2005
  • fDate
    28-30 Sept. 2005
  • Lastpage
    9
  • Abstract
    In this paper we study a fundamental design problem for 2-level reconfigurable architectures (which are a special case of hyperreconfigurable architectures). On the lower reconfiguration level such architectures perform ordinary dynamic reconfiguration operations. On the upper level they can dynamically change the reconfiguration capabilities of the reconfigurable resources that are available for the lower level reconfiguration. Resources which have reduced reconfiguration capabilities can be reconfigured fast because not much reconfiguration information is needed to determine the new states of the resources. Whereas resources with larger reconfiguration capabilities have the advantage of higher flexibility but need more reconfiguration information. So far 2-level reconfigurable architectures have been used mainly as a concept to study the potential and limits of dynamic reconfiguration from a general point of view and based on formal models. The design problem that is addressed here is to find the best level of granularity that should be provided by the architecture for the upper level reconfiguration operations. A fine granularity allows the upper level reconfiguration operations to adapt the reconfiguration capabilities of the resources such that: i) the provided flexibility matches closely the actual needs, and ii) not too much reconfiguration information is needed. A possible disadvantage of a fine granularity is that the upper level reconfiguration operations themselves need more reconfiguration information. We give a formal definition of the corresponding hypercontext design problem (HDP) and show theoretical results on the complexity of this problem. Moreover we describe a heuristic for solving the HDP and study three example problems
  • Keywords
    logic design; reconfigurable architectures; dynamic reconfiguration operations; fine granularity; hypercontext design problem; lower level reconfiguration; two-level reconfigurable architectures; Computer architecture; Computer science; Field programmable gate arrays; Parallel processing; Reconfigurable architectures; Routing; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reconfigurable Computing and FPGAs, 2005. ReConFig 2005. International Conference on
  • Conference_Location
    Puebla City
  • Print_ISBN
    0-7695-2456-7
  • Type

    conf

  • DOI
    10.1109/RECONFIG.2005.26
  • Filename
    1592491