Title :
Small-Signal Analysis and Modeling of Asymmetric Source/Drain Parasitic Resistances for DRAM Access Transistors in Low-Power Applications
Author :
Kim, Y.P. ; Ulrich, Matthew ; Vaidyanathan, Praveen ; Ananthan, Venkat ; Mouli, Chandra ; Parekh, Kunal
Author_Institution :
R&D Process Dev., Micron Technol. Inc., Boise, ID
Abstract :
The small-signal conductance technique was extended to extract asymmetric source/drain parasitic resistances. It was also applied in order to analyze the tWR delay of DRAM cell transistors in production and to develop a non-planar cell transistor such as recessed access device (RAD) for low-power DRAM cells. Factors limiting the drive current for planar and non-planar access transistors in the low-power DRAM cells were discussed
Keywords :
DRAM chips; electric resistance; field effect transistors; integrated circuit modelling; DRAM cell transistors; RAD; asymmetric source-drain parasitic resistances; low-power applications; nonplanar cell transistor; planar access transistors; recessed access device; small-signal conductance technique; small-signal modeling; tWR delay; Data mining; Delay; Drives; Equations; Manufacturing; Monitoring; Production; Random access memory; Research and development; Threshold voltage;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2006 International Conference on
Conference_Location :
Monterey, CA
Print_ISBN :
1-4244-0404-5
DOI :
10.1109/SISPAD.2006.282856
