Title :
Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus
Author :
Ching, Mai Y. ; Boon, Ang T. ; Yeong, Chin K. ; Rokhani, Fakhrul Z.
Author_Institution :
Dept. of Comput. & Commun. Syst. Eng., Univ. Putra Malaysia, Serdang, Malaysia
Abstract :
In this paper, the technique of optimal interconnects width and spacing is analyzed to reduce the area, delay and area-delay-product of multi-level signaling on-chip bus. To capture the delay impact from cross-coupling capacitance in the deep sub-micron on-chip bus, the Miller Capacitance Factor (MCF) for 4-level signals is developed. Results show that our proposed technique reveals the trade-off between bus area and delay to achieve the optimized bus configuration.
Keywords :
circuit optimisation; delays; integrated circuit design; integrated circuit interconnections; Miller capacitance factor; area-delay optimization; cross coupling capacitance; deep submicron on-chip bus; interconnect area; multi level signaling on-chip bus; optimal interconnect spacing; optimal interconnects width; Capacitance; Coupling capacitance; Multilevel signaling; interconnect delay; interconnect optimization;
Conference_Titel :
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4244-7454-7
DOI :
10.1109/APCCAS.2010.5775086
