DocumentCode
3233422
Title
A fast CRAM SEU error detection scheme for FPGAs
Author
Jong Kiun Kiet ; Tan Jun Pin ; Ang Boon Jin
Author_Institution
Altera Corp. (M) Sdn. Bhd., Bayan Lepa, Malaysia
fYear
2010
fDate
6-9 Dec. 2010
Firstpage
995
Lastpage
998
Abstract
This paper proposes a scheme that can detect SEU errors occurring in an FPGA configuration SRAM cell (CRAM) in a time-efficient manner (>;40X faster or<;2 ms). The concept and design implementation of the proposed scheme is described in detail. This is a low-cost solution as most of the implementation reuses existing circuits. In addition, the benefits of the proposed schemes are discussed.
Keywords
SRAM chips; field programmable gate arrays; FPGA; configuration SRAM cell; fast CRAM SEU error detection scheme; single event upsets; Field programmable gate arrays; CRAM; Error Detection; FPGA; LFSR; MISR; SEU;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on
Conference_Location
Kuala Lumpur
Print_ISBN
978-1-4244-7454-7
Type
conf
DOI
10.1109/APCCAS.2010.5775097
Filename
5775097
Link To Document