DocumentCode
3233491
Title
An FPGA-based coprocessor for the SPHINX speech recognition system: early experiences
Author
Marcus, Guillermo ; Nolazco-Flores, J.A.
Author_Institution
Lehrstuhl fur Informatik V, Univ. Mannheim
fYear
2005
fDate
28-30 Sept. 2005
Lastpage
27
Abstract
A FPGA based hardware coprocessor for the SPHINX Speech Recognition System is presented. The coprocessor operates at 66MHz and implements a critical part of the Baum-Welch Algorithm to assist in the Gaussian probability calculations, currently with a peak performance of 264 MFlops. Results are presented in comparison with a Xeon 2.66GHz computer and a similar ASIC project, together with guidelines for future development
Keywords
coprocessors; digital signal processing chips; field programmable gate arrays; speech recognition; 66 MHz; Baum-Welch algorithm; FPGA-based coprocessor; Gaussian probability calculations; SPHINX speech recognition system; Xeon computer; hardware coprocessor; Application specific integrated circuits; Coprocessors; Databases; Field programmable gate arrays; Guidelines; Hardware; Hidden Markov models; Iterative algorithms; Power system modeling; Speech recognition;
fLanguage
English
Publisher
ieee
Conference_Titel
Reconfigurable Computing and FPGAs, 2005. ReConFig 2005. International Conference on
Conference_Location
Puebla City
Print_ISBN
0-7695-2456-7
Type
conf
DOI
10.1109/RECONFIG.2005.10
Filename
1592509
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