A tripartite system level design approach for design space exploration

Abstract-In this paper a system level design approach is presented, which reduces the effort of integrating low level tools for the evaluation of different solutions during design space exploration. Thereby, low level estimation tools can be utilized for a fast and accurate estimation of the power consumption of different HW/SW architectures. The proposed design flow extends the known separation of communication and computation to a tripartite design approach. By separately modeling complex data structures, it is possible to design parts that specify computation directly synthesizable and compilable without major changes. Communication parts and complex data structures are taken from a library or refined manually. Using this approach, the way from a system level model to an actual HW/SW implementation is accelerated and the application of low level power estimation tools becomes possible. The benefits of this new design approach are demonstrated by the generation of different solutions of a test system of an audio resampler for VoIP systems. Seven different HW/SW solutions are compared concerning their power consumption, latency, and area.