Title :
Simulation of Multiple Gate FinFET Device Gate Capacitance and Performance with Gate Length and Pitch Scaling
Author :
Zhao, Hui ; Agrawal, Naveen ; Javier, Ramos ; Rustagi, Subhash C. ; Jurczak, M. ; Yeo, Yee Chia ; Samudra, Ganesh S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore
Abstract :
In this work, we simulate silicon-on-insulator (SOI) multiple gate FinFET (MuGFET) with the design targeting for the ITRS 2004 specifications for NMOSFET. A detailed fully 3D simulation and analysis of the parasitic capacitances is performed for the first time to study the impact of scaling and pitch spacing. Unlike planar devices, FinFET scaling does not always result in a straightforward performance improvement due to the current crowding effect and series resistance
Keywords :
MOSFET; semiconductor device models; silicon-on-insulator; 3D simulation; MuGFET; NMOSFET; SOI; current crowding effect; multiple gate FinFET; pitch scaling; silicon-on-insulator; Dielectric measurements; Doping profiles; FinFETs; Laboratories; MOSFET circuits; Microelectronics; Parasitic capacitance; Predictive models; Semiconductor process modeling; Silicon on insulator technology; 3D simulation; FinFET; Multi-gate; capacitance; scaling;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2006 International Conference on
Conference_Location :
Monterey, CA
Print_ISBN :
1-4244-0404-5
DOI :
10.1109/SISPAD.2006.282883
