SystemC architectural transaction level modelling for large NoCs

Network-on-chip (NoC) has been accepted as a viable solution to cope with ever increasing communication demand in future many-core system-on-chips with hundreds to thousands of heterogeneous cores. Developing and manufacturing these complex NoCs are not feasible without early system validation by using high-level simulation. This paper proposes an architectural transaction level modelling technique to model many-core NoCs which is suitable for early system evaluation. The experimental results show an improvement of up to 38% in simulation time compared to the model in which each process uses SystemC methods.