Bottom-up verification methodology for CMOS photonic linear heterogeneous system

A typical CMOS photonic circuit may comprise analog, digital and optical devices. To simulate it, a common simulation environment for electrical/optical systems is necessary. In this article, a simulation methodology for CMOS photonic heterogeneous system has been proposed. Using hardware description language, we create behavioral models for optical devices with S-matrix formalism. The challenges in model implementation have been addressed, such as large-size vector representation at model ports and complex matrix calculation. And a Verilog-AMS + VPI simulation strategy is proposed to solve the simulation issues. Finally, the proposed method is applied to bottom-up verification of a micro-ring array, and the simulation result matches well with brute force simulation, while the simulation time is largely reduced.