Title :
Scaling Limit of CMOS Supply Voltage from Noise Margin Considerations
Author :
Liu, Minjian ; Cai, Ming ; Taur, Yuan
Author_Institution :
California Univ., San Diego, La Jolla, CA
Abstract :
This paper investigates the scaling limit of CMOS supply voltage for maintaining the noise margin of NAND circuits subject to process tolerance induced threshold voltage variation. It is shown that for high performance (Vt/Vdd<1/3) decananometer CMOS devices with plusmn20% gate length tolerance and corresponding short-channel threshold roll-off, the supply voltage cannot be lower than 0.5 V in order to keep logic state consistency in the worst-case switching scenario
Keywords :
CMOS integrated circuits; NAND circuits; NAND circuits; decananometer CMOS devices; noise margin; process tolerance; short-channel threshold roll-off; worst-case switching; CMOS logic circuits; CMOS process; CMOS technology; Circuit noise; Inverters; Logic circuits; Logic devices; MOSFETs; Power supplies; Threshold voltage;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2006 International Conference on
Conference_Location :
Monterey, CA
Print_ISBN :
1-4244-0404-5
DOI :
10.1109/SISPAD.2006.282892
