Title :
Power/Performance Based Scalability Comparisons between Conventional and Novel Transistors Down to 32nm Technology Node
Author :
Kapur, P. ; Shenoy, R.S. ; Saraswat, K.C.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA
Abstract :
We quantify and compare the scalability of bulk, partially depleted SOI, and double gate transistors with and without high-k gate dielectric down to 32 nm technology node in terms of globally optimized power/performance curves. The novelty of work is in that it provides a quantitative tool to determine the suitable insertion point for novel transistor schemes. It also addresses optimum supply/threshold voltage, gate dielectric thickness, and doping concentration scaling, unique to different devices and circuit functional blocks
Keywords :
field effect transistors; high-k dielectric thin films; semiconductor doping; silicon-on-insulator; 32 nm; 32 nm technology node; doping concentration scaling; double gate transistors; high-k gate dielectric; partially depleted SOI; power-performance based scalability; silicon-on-insulator; Analytical models; Circuits; Computational Intelligence Society; Delay; Dielectric devices; Doping; Gate leakage; High K dielectric materials; Scalability; Threshold voltage;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2006 International Conference on
Conference_Location :
Monterey, CA
Print_ISBN :
1-4244-0404-5
DOI :
10.1109/SISPAD.2006.282893
