• DocumentCode
    3234258
  • Title

    A new multi-processor architecture for parallel lazy cyclic reference counting

  • Author

    Lins, Rafael Dueire

  • Author_Institution
    Dept. de Eletronica e Sistemas, Univ. Fed. de Pernambuco, Recife, Brazil
  • fYear
    2005
  • fDate
    24-27 Oct. 2005
  • Firstpage
    35
  • Lastpage
    42
  • Abstract
    Reference counting is the memory management technique of most widespread use today. This paper presents a new multi-processor architecture for parallel cyclic reference counting. In this architecture, there is no direct mutator-collector communication and synchronization is kept minimal.
  • Keywords
    multiprocessing systems; parallel architectures; storage management; memory management technique; multiprocessor architecture; mutator-collector communication; mutator-collector synchronization; parallel lazy cyclic reference counting; Algorithm design and analysis; Computer languages; Data structures; Heuristic algorithms; Java; Memory management; Parallel architectures; Parallel programming; Programming profession; Virtual machining;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture and High Performance Computing, 2005. SBAC-PAD 2005. 17th International Symposium on
  • ISSN
    1550-6533
  • Print_ISBN
    0-7695-2446-X
  • Type

    conf

  • DOI
    10.1109/CAHPC.2005.6
  • Filename
    1592554
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3234258