DocumentCode
3234448
Title
Cooperation of neighboring PEs in clustered architectures
Author
Sato, Yukinori ; Suzuki, Ken-ichi ; Nakamura, Tadao
Author_Institution
Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
fYear
2005
fDate
24-27 Oct. 2005
Firstpage
134
Lastpage
141
Abstract
Clustered architectures which intend to process data within a localized PE are one of the approaches to increase the performance under the difficulties of the wire delay problems. The performance of clustered architectures depends on the amount of parallel execution of instructions and the amount of inter-PE communication to synchronize dependent instructions. In this paper, we propose an arrangement of PEs cooperating with the adjacent PEs by means of adding communication structures between the adjacent PEs in order to relax the inter-PE communication and workload imbalance in an effective manner. We evaluate the proposed configurations and compare them with the existing one so far considered. The results show that the proposed adjacent forwarding network configuration with the instruction steering scheme that concerns both the register fanout and available free register can achieve higher instructions per clock (IPC) with the small number of registers per PE than the other configurations.
Keywords
multiprocessing systems; resource allocation; workstation clusters; clustered architecture; instruction steering; interprocessing element communication; localized processing element; network configuration; parallel execution; synchronize dependent instruction; wire delay; workload imbalance; CMOS technology; Computer architecture; Decoding; Degradation; Delay; Hardware; Logic; Microarchitecture; Synchronization; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture and High Performance Computing, 2005. SBAC-PAD 2005. 17th International Symposium on
ISSN
1550-6533
Print_ISBN
0-7695-2446-X
Type
conf
DOI
10.1109/CAHPC.2005.21
Filename
1592566
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