DocumentCode :
3234472
Title :
A Full 3D TCAD Simulation Study of Line-Width Roughness Effects in 65 nm Technology
Author :
Sponton, Luca ; Bomholt, L. ; Pramanik, Dipankar ; Fichtner, Wolfgang
Author_Institution :
Integrated Syst. Lab., ETH, Zurich
fYear :
2006
fDate :
6-8 Sept. 2006
Firstpage :
377
Lastpage :
380
Abstract :
For the 65 nm technology node and beyond, new manufacturability problems are arising that strongly impact device and circuit behavior. Among these problems, line-edge and line-width roughness (LER and LWR) are of particular interest as dominant issues affecting parametric yield. In this paper, we investigate LWR effects by applying latest generation, full 3D TCAD technology including lithography simulation. In addition, our results answer open questions concerning the applicability of 2D slicing approximations vis a vis a 3D modeling effort. While LWR has been investigated by TCAD before, our methodology includes a full 3D process simulation (including lithography) without simplifications to generate the final transistor structures
Keywords :
lithography; semiconductor process modelling; technology CAD (electronics); 3D TCAD simulation study; 65 nm; LWR effect; line-width roughness; lithography simulation; transistor structure; Circuit simulation; Integrated circuit manufacture; Integrated circuit technology; Laboratories; Lithography; MOSFETs; Printing; Process design; Shape; Virtual manufacturing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2006 International Conference on
Conference_Location :
Monterey, CA
Print_ISBN :
1-4244-0404-5
Type :
conf
DOI :
10.1109/SISPAD.2006.282913
Filename :
4061656
Link To Document :
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