Title :
Examination of shallow trench isolation for SOI
Author :
Brady, F. ; Wright, S. ; Houston, G.
Author_Institution :
Lockheed Martin Fed. Syst., Manassas, VA, USA
fDate :
30 Sep-3 Oct 1996
Abstract :
Improvements in device isolation are necessary to meet the demand for increasing transistor layout density for future VLSI technology generations. Efforts to make these improvements are focused primarily on advanced LOCOS and shallow trench isolation (STI) techniques. At Loral, we are currently pursuing STI for our next generation bulk technology. In this work, we adapt the bulk STI process to SOI, and examine some of the issues encountered. STI is integrated with 0.5 μm, fully-depleted, accumulation mode devices. N-channel devices are fabricated and device parametrics, reliability, and radiation effects are investigated. The goal for this work was to have functional 0.7 μm wide (as-drawn) devices
Keywords :
CMOS integrated circuits; VLSI; integrated circuit reliability; integrated circuit technology; isolation technology; radiation effects; silicon-on-insulator; 0.7 micron; SOI; Si; VLSI technology; bulk STI process; fully-depleted accumulation mode devices; radiation effects; reliability; shallow trench isolation; transistor layout density; Degradation; Etching; Radiation effects; Resists; Semiconductor films; Silicon; Substrates; Threshold voltage; Tin; Very large scale integration;
Conference_Titel :
SOI Conference, 1996. Proceedings., 1996 IEEE International
Conference_Location :
Sanibel Island, FL
Print_ISBN :
0-7803-3315-2
DOI :
10.1109/SOI.1996.552509
