Implementation and analysis of speculative flow control for on-chip interconnection network

We have built a model for credit-based flow control with speculation and discuss the performance evaluation in this paper. Speculative flow control has been proposed in [1]. First, we design and implement this flow control mechanic in Verilog HDL. In order to make performance evaluation, we set up a 4-by-4 mesh network model using credit-based flow control with and without speculation by Verilog HDL in RTL level. We tune some parameters of the network model, such as buffer size, delay time between adjacent nodes and speculated packet size for performance evaluation. We also devise two types of traffic model on mesh network to show the influence of traffic on the network. Hardware cost in FPGA or ASIC is also presented.