Test patterns for ICs that are both secure and have very high coverage

Historically, test engineers have used various Design-for-Test techniques to enhance access to internal design logic thus simplifying test generation and defect detection. Techniques such as scan chain insertion greatly increase the test programpsilas ability to control and observe nodes within the functional design through primary pins and result in very high test coverage. For most test engineers, therepsilas very little tolerance for low test quality. Test patterns with high fault detection are essential to minimizing the number of defective parts that escape test and are shipped to end customers. The goal is to reduce this metric, measured in defective parts in million (DPM), as much as possible. However, the ever-increasing need to control and observe functional nodes is in direct conflict with requirements of secure applications. In this paper, we will explore the techniques currently in use for testing devices designed for secure application and review the benefits and challenges of each available solution. Test approaches such as compression and reduced pin count testing that enable both the testability and the high level of security needed by secure applications will be scrutinized as well as traditional test techniques such as functional test and traditional scan.