Efficient diagnosable design of the IEEE P1500 architecture for SoC testing

System-on-a-chip (SoC) as a platform for system integration has been used extensively in modern VLSI design. The IEEE P1500 has been proposed as a standard for the challenging SoC testing problem. In order to improve the correctness of SoC testing, the IEEE P1500 hardware itself should be tested and diagnosed first before using it. This paper proposes an efficient design-for-diagnosability architecture for the IEEE P1500 and evaluates its performance. Effective diagnosis procedures are presented and the response sequences of the output are analyzed for fault diagnosis. With our proposed designs, single stuck-at faults and fault location can be efficiently determined.