Hardware Accelerator for Dictionary-Based Compression of MMP Algorithm

Author

de L Reis, Vanderson ; Moreno, Edward David ; De Carvalho, Murilo B.

fYear

2010

fDate

27-30 Oct. 2010

Firstpage

48

Lastpage

55

Abstract

The MMP is an algorithm for image compression which uses the multiscale method of recurrent patterns, based on dictionary. The MMP has compression ratio at the same level of others compression algorithms which are based on transforms, having been detached to images with high frequency, however its execution time has been shown high, by repeated searches of these patterns in dictionaries. In this paper we propose a parallel and dedication hardware to accelerate the execution of MMP, and it is implemented in FPGA, which performs the critical function in 340ns, achieving a speedup of 300 over software version.

Keywords

data compression; dictionaries; embedded systems; field programmable gate arrays; image coding; parallel architectures; FPGA; MMP algorithm; dictionary based compression; hardware accelerator; image compression; software version; Field programmable gate arrays; Hardware; Image coding; Pixel; Software; Transform coding; Wavelet transforms; Embedded Systems; FPGA; Image Compression; Partition H/S; Pattern Multiscale Matching and Recurring;

fLanguage

English

Publisher

ieee

Conference_Titel

Computing Systems (WSCAD-SCC), 2010 11th Symposium on

Conference_Location

Petropolis

Print_ISBN

978-1-4244-8974-9

Electronic_ISBN

978-0-7695-4274-4

Type

conf

DOI

10.1109/WSCAD-SCC.2010.11

Filename

5645443