Hardware Accelerator for Dictionary-Based Compression of MMP Algorithm

The MMP is an algorithm for image compression which uses the multiscale method of recurrent patterns, based on dictionary. The MMP has compression ratio at the same level of others compression algorithms which are based on transforms, having been detached to images with high frequency, however its execution time has been shown high, by repeated searches of these patterns in dictionaries. In this paper we propose a parallel and dedication hardware to accelerate the execution of MMP, and it is implemented in FPGA, which performs the critical function in 340ns, achieving a speedup of 300 over software version.