Title :
Design of an ASIP IDEA crypto processor
Author :
Mirzaee, Reza Faghih ; Eshghi, Mohammad
Author_Institution :
Dept. of Comput. Eng., Islamic Azad Univ., Tehran, Iran
Abstract :
A New architecture is presented in this paper for International Data Encryption Algorithm based on Application Specific Instruction set Processors platform. Designing process is explained comprehensively for all the main components within the crypto processor core. The basic structure is developed in order to reduce the required clock cycles for the main specific instruction which encrypts/decrypts input data. The complete instruction set is written in Register Transform Language. Then, VHDL code is utilized to test the proposed design.
Keywords :
cryptography; hardware description languages; instruction sets; microprocessor chips; ASIP IDEA crypto processor design; VHDL code; application specific instruction set processors platform; clock cycles reduction; crypto processor core; international data encryption algorithm; register transform language; Algorithm design and analysis; Clocks; Encryption; Memory management; Registers; ASIP; Crypto Processor; Cryptography; DPU; IDEA; RTL; Register and ALU Configuration;
Conference_Titel :
Networked Embedded Systems for Enterprise Applications (NESEA), 2011 IEEE 2nd International Conference on
Conference_Location :
Fremantle, WA
Print_ISBN :
978-1-4673-0495-5
DOI :
10.1109/NESEA.2011.6144954
