• DocumentCode
    3235567
  • Title

    Comparison of heuristic algorithms for variable partitioning in circuit implementation

  • Author

    Muthukumar, Venkatesan ; Selvaraj, Henry

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Nevada Univ., Las Vegas, NV, USA
  • fYear
    2003
  • fDate
    4-8 Jan. 2003
  • Firstpage
    51
  • Lastpage
    57
  • Abstract
    Functional decomposition is a process of splitting a complex circuit into smaller sub-circuits. This paper deals with the problem of determining the set of best free and bound variables (variable partitioning problem) for disjoint (disjoint serial) decomposition, such that the decomposed circuits are smaller in size and its truth table representation have maximal don´t cares. A novel pruned breadth first search (PBFS/IPBFS) approach is proposed to determine the set of good variable partitions with minimal time and computational complexity. The heuristics proposed minimize the size of the sub functions. The proposed approach has been successfully implemented and test with MCNC and Espresso benchmarks.
  • Keywords
    logic CAD; logic partitioning; tree searching; PBFS/IPBFS; circuit decomposition; disjoint decomposition; disjoint serial decomposition; functional decomposition; heuristic algorithm; improved pruned breadth first search; logic synthesis; pruned breadth first search; truth table; variable partitioning; Benchmark testing; Circuit synthesis; Circuit testing; Computational complexity; Cost function; Field programmable gate arrays; Heuristic algorithms; Input variables; Partitioning algorithms; Search methods;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2003. Proceedings. 16th International Conference on
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-1868-0
  • Type

    conf

  • DOI
    10.1109/ICVD.2003.1183114
  • Filename
    1183114