Title :
Performance of a low power fully-depleted deep submicron SOI technology and its extension to 0.15 μm
Author :
Burns, J.A. ; Keast, C.L. ; Knecht, J.M. ; Kunz, R.R. ; Palmateer, S.C. ; Cann, S. ; Soares, A. ; Shaver, D.C.
Author_Institution :
Lincoln Lab., MIT, Lexington, MA, USA
fDate :
30 Sep-3 Oct 1996
Abstract :
Lincoln Laboratory has developed a fully-depleted silicon-on-insulator (SOI) technology to build integrated circuits designed for very low power operation and fabricated at the limits of optical lithography. A 0.25 μm (drawn gate length) fully-depleted SOI CMOS process technology was established using 248-nm optical lithography for initial process demonstrations, and to identify nonlithographic process integration pinch points and SOI material related issues. Design rules and SPICE parameters have been issued for the 0.25 μm technology and a multi-project chip set assembled. The process technology has been adapted to Lincoln´s 193-nm step-and-scan tool to fabricate O.2 μm circuits and provide the first application of 193-nm lithography to a complete CMOS process. This paper describes the performance characteristics of the technology and the enhancements necessary to extend it to 0.15 μm
Keywords :
CMOS integrated circuits; VLSI; integrated circuit measurement; integrated circuit technology; photolithography; silicon-on-insulator; 0.15 to 0.2 micron; 193 nm; 248 nm; CMOS integrated circuits; CMOS process technology; SPICE parameters; Si; drawn gate length; fully-depleted deep submicron SOI technology; multi-project chip set; optical lithography; process integration pinch points; CMOS process; CMOS technology; Integrated circuit technology; Integrated optics; Laboratories; Lithography; Optical design; Optical materials; Photonic integrated circuits; Silicon on insulator technology;
Conference_Titel :
SOI Conference, 1996. Proceedings., 1996 IEEE International
Conference_Location :
Sanibel Island, FL
Print_ISBN :
0-7803-3315-2
DOI :
10.1109/SOI.1996.552514
