A functional enhancement methodology to JTAG controller in complex SOC

Based on one complex SOC chip, one functional enhancement methodology to standard IEEE P1149.1 JTAG controller is proposed in this paper. With the enhanced features, all test functions including stuck-at scan, at-speed scan, memory BIST and high-speed physical layer tests can be controlled by the JTAG controller besides traditional boundary scan tests, and further on-chip debug features are also integrated in this enhanced JTAG controller. Therefore, the chip costs can be reduced, and the software development and debug can be facilitated with the enhanced JTAG controller.