Title :
An Extended SVD-based Terminal and Model Order Reduction Algorithm
Author :
Liu, Pu ; Tan, Sheldon X D ; Yan, Boyuan ; McGaughy, Bruce
Author_Institution :
Dept. of Electr. Eng., California Univ., Riverside, CA
Abstract :
The paper proposes a new combined terminal and model order reduction method for compact modeling of interconnect circuits. The new method extends the existing SVDMOR method by using higher order moment information for terminal responses during the terminal reduction and by applying separate SVD low-rank approximations on input and output terminals respectively. This is in contrast to SVDMOR method where input and output terminal responses are SVD approximated at the same time, which can lead to large error when the numbers of inputs and outputs are quite different. We analyze the passivity requirement for combined terminal and model order reduction and show the passivity enforcement may significantly hamper the terminal reduction effects. We also improve the computation efficiency of SVDMOR. Our experimental results show that ESVDMOR outperforms the SVDMOR in terms of accuracy for the similar reduced model sizes in a number of interconnect circuits when the input and output terminals are different
Keywords :
RLC circuits; circuit CAD; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; reduced order systems; singular value decomposition; SVD low-rank approximation; SVD-based terminal model order reduction algorithm; interconnect circuit compact modeling; terminal response; Clocks; Complexity theory; Degradation; Integrated circuit interconnections; RLC circuits; Reduced order systems; Timing; Transfer functions;
Conference_Titel :
Behavioral Modeling and Simulation Workshop, Proceedings of the 2006 IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-9742-8
DOI :
10.1109/BMAS.2006.283468
