Automating control and evaluation of FPGA testing using SJ BIST®

SJ BIST^reg is a method to detect intermittent faults in ball grid array (BGA) packages of field programmable gate arrays (FPGAs). Failure of monitored I/O pins on operational, fully-programmed FPGAs is detected and reported by SJ BIST to provide positive indication of damage to one or more I/O solder-joint networks of an FPGA on an electronic digital board. The board can then be replaced before accumulated fatigue damage results in intermittent or long-lasting operational faults. This paper presents the test procedures to provide a lap-top-based test bed for controlling SJ BIST in the FPGAs on those evaluation boards. The procedures include using a Spartan 3trade development kit, a verilog-based test program, and a MATLAB^reg program for collecting, saving and displaying test data, all of which reside on a lap-top PC with a serial data port. The FPGA on a HALT evaluation board is programmed with SJ BIST (patent pending).