Fast gate-level simulation and power analysis for high performance microprocessor

With the advance of VLSI technology, power consumption of chips has become a major concern in the state of art CMOS circuits design. Among all kinds of previous power analysis methods, the gate-level power analysis can give a relatively accurate result and has been commonly used. However, the simulation speed is very low due to large amount switching activity records for all gate-level cells. In this paper, we proposed a novel method to accelerate gate-level power simulation and estimation. The experimental results based on actual gate-level netlist of Godson-2 processor have shown that the proposed method can improve simulation speed by about 20 times compared with traditional gate-level power calculation, and the error of power analysis result is less than 5%.