A new approach to analyze a sub-micron CMOS inverter

Author

Pattanaik, Manisha ; Banerjee, Swapna

Author_Institution

Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, India

fYear

2003

fDate

4-8 Jan. 2003

Firstpage

116

Lastpage

121

Abstract

An analytical model is proposed for submicron CMOS devices based on Thornber´s scaling law where the field dependent mobility and carrier velocity saturation are treated independently. Comparison of simulated results with the experimental results of I∼V data for sub and deep sub micrometer MOSFETs down to 0.09 μm effective gate length demonstrates the accuracy of the model. A sub micron CMOS (0.2 μm technology) inverter is analyzed by using the proposed model. Results show that the calculated propagation delay and output voltage waveform are in good agreement with Spectre simulation results.

Keywords

CMOS logic circuits; MOSFET; carrier mobility; circuit simulation; integrated circuit modelling; logic gates; semiconductor device models; 0.09 micron; 0.2 micron; CMOS inverter; I/V characteristics; MOSFET; Thornber scaling law; carrier velocity saturation; effective gate length; field dependent mobility; output voltage waveform; propagation delay; Analytical models; CMOS logic circuits; CMOS technology; Circuit simulation; Degradation; Inverters; MOSFETs; Particle scattering; Propagation delay; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2003. Proceedings. 16th International Conference on

ISSN

1063-9667

Print_ISBN

0-7695-1868-0

Type

conf

DOI

10.1109/ICVD.2003.1183124

Filename

1183124