Title :
A Verilog Mixed Signal Model of a 10-bit Pipeline Analog-to-Digital Converter
Author :
Mentzer, Jeff ; Wey, Todd
Author_Institution :
Lafayette Coll.
Abstract :
A mixed-signal model of a 10-bit pipeline ADC is developed using the Verilog language. Transient results for individual cells and the overall converter are calculated by solving the characteristic differential equations using an event driven forward Euler numerical solver. The model includes nonlinearities within the amplifier such as capacitor mismatch and slew rate limiting. Post-processing is done in Matlab. The overall goal of this work is to develop a mixed-signal model to verify and identify design flaws based on ADC input/output tests
Keywords :
analogue-digital conversion; differential equations; hardware description languages; mixed analogue-digital integrated circuits; switched capacitor networks; 10-bit pipeline; Euler numerical solver; Matlab; Verilog mixed signal model; analog-to-digital converter; Analog-digital conversion; Capacitors; Clocks; Hardware design languages; Mathematical model; Pipelines; Sampling methods; Switches; Switching circuits; Voltage;
Conference_Titel :
Behavioral Modeling and Simulation Workshop, Proceedings of the 2006 IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-9742-8
DOI :
10.1109/BMAS.2006.283480
