DocumentCode :
3235975
Title :
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
Author :
Krishnan, Rohini ; Gangwal, O.P. ; Eijndhoven, Jos V. ; Kumar, Anshul
Author_Institution :
Philips Res. Labs., Eindhoven, Netherlands
fYear :
2003
fDate :
4-8 Jan. 2003
Firstpage :
177
Lastpage :
182
Abstract :
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processor scales with the size of the input blocks varying from 7 cycles for an 1×1 block to 38 cycles for an 8 × 8 block. This scalability is possible because the processor has input data dependant control by which it can exploit the reduced computational needs of sub-sampled blocks and blocks of smaller sizes to work in lesser cycles. This is a very useful feature for MPEG and HDTV decoders and has hitherto not been exploited. Clocking at 150 Mhz, the processor satisfies the high sample rate requirement of dual MPEG stream HD decoding with a picture size of 1920 × 1080 at 30 frames per second. Fixed word length and accuracy simulations of our design shows that it conforms to the accuracy specifications of the CCITT standard within a 16 bit data path. A methodology based on architecture level synthesis is used to design the VLIW processor core. The VLIW design exploits the Instruction Level Parallelism present in the DCT/IDCT application, efficiently. The processor core is characterised by an area of 0.834 mm sq. and a frequency of 150 Mhz in 0.18 micron CMOS technology.
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; decoding; digital signal processing chips; discrete cosine transforms; high definition television; parallel architectures; 0.18 micron; 150 MHz; 16 bit; 2D DCT/IDCT application specific VLIW processor; CMOS technology; HDTV decoder; MPEG decoder; architecture level synthesis; instruction level parallelism; scaled block; sub-sampled block; CMOS technology; Clocks; Decoding; Delay; Discrete cosine transforms; HDTV; High definition video; Scalability; Size control; VLIW;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2003. Proceedings. 16th International Conference on
ISSN :
1063-9667
Print_ISBN :
0-7695-1868-0
Type :
conf
DOI :
10.1109/ICVD.2003.1183133
Filename :
1183133
Link To Document :
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