Functional Verification of Radio Frequency SoCs using Mixed-Mode and Mixed-Domain Simulations

The main focus of this work is the functional verification of radio frequency (RF) transceivers and RF systems on chip (SoCs). The use of enhanced baseband behavioral description models for an industrial available multiband, low IF GSM receiver is demonstrated. The necessity of functional verification when dealing with complex baseband signals and mixing operations with high/low sideband possibilities is shown. Future demands on language constructs and their implementations into the design flow are presented. Fundamental simulation comparisons for different implementation levels and proposals for new constructs to ensure functionality and connectivity between advanced behavioral description level and transistor schematics are made. This paper concludes with a suggestion for an extension of the Verilog-HDL-family to aid SoC designers in their effort to shorten the time to market and demonstrates the possible benefits of upcoming systemVerilog constructs