Hierarchical architecture for fast CMOS SRAMs

A new concept for the design of fast SRAMs is described, introducing a highly hierarchical architecture with short word and bit lines. Computational results based on layouts in a standard 1-μm technology yield a 9-ns access time for a 64 K SRAM. The authors estimate that the access time is at least 50% longer in a conventional architecture, while the area is about 30% smaller. No address transition detection circuitry or other internal timing is required for the hierarchical approach. No critical analog circuit parts are applied. The new concept shows little sensitivity with respect to technology variations and can also be used for future technology generations with reduced supply voltage