D-Power: A VHDL Dynamic Power Estimation Tool for Superscalar Architectures - Cache Hierarchy and Fetch Stage

Technological innovations constantly emerge in computer systems. Its primary focus is on the improvement of performance. One way to improve performance is to increase the hardware. However, this increase in hardware has its implications, like a larger area required on the chip and a consequent increase in power consumption. This boost in power consumption raises heat dissipation, difficult cooling and circuit expansion, among other factors. Because of these problems, the power consumption is target of several studies which try to estimate it and find alternatives to reduce it before the design of the chip. In this context, this paper presents the D-Power tool, a tool described in VHDL designed to estimate dynamic power consumption in components of the fetch stage and cache hierarchy in a superscalar architecture. Based on the entries parameters, the tool is able to verify, among several models of components, which one are more advantageous in relation to power consumption and performance.