Protocol Aware ATE with FPGA-based hardware

In his paper last year, Andrew Evans of Broadcom Corporation outlined the exciting concept of Protocol Aware ATE, and even made the plea for ATE vendors to ldquomake a broad paradigm shift in ATE architecture that will enable true system level testing as part of the production test flow and methodology.rdquo [1] This concept of system level testing requires intelligent test equipment to have integrated communication protocols for better simulation and emulation of the native environment around the device-under-test (DUT). Field programmable gate array (FPGA) technology is the answer to achieving this level of hardware customization, but presents many challenges with regard to FPGA implementation, custom hardware integration and software programming interfaces. This paper will discuss the will discuss the topic of protocol aware testing and how to achieve aspects of it with COTS FPGA hardware. It will explore important hardware architectures that are well suited for this concept which include FPGA-based boards with a standard PC interfaces, as well as the increasing need for higher level design tools. Protocol aware ATE is an important step to increase the intelligence of the next generation test system, resulting in increased productivity through hardware abstraction at the protocol level.