VLSI implementation of online digital watermarking technique with difference encoding for 8-bit gray scale images

Author

Garimella, Annajirao ; Satyanarayana, M.V.V. ; Satish Kumar, R. ; Murugesh, P.S. ; Niranjan, U.C.

Author_Institution

Manipal Acad. of Higher Educ., India

fYear

2003

fDate

4-8 Jan. 2003

Firstpage

283

Lastpage

288

Abstract

Digital watermarking is a technique of embedding imperceptible information into digital documents. In this paper, a VLSI implementation of the digital watermarking technique is presented for 8 bit gray scale images. This implementation of fragile invisible watermarking is carried out in the spatial domain. The standard ASIC design flow for a 0.13 μm CMOS technology has been used to implement the algorithm. The area of the chip is 3453×3453 μm² and the power consumption is 37.6 μW.

Keywords

CMOS logic circuits; VLSI; application specific integrated circuits; circuit simulation; cryptography; image coding; integrated circuit design; logic design; logic simulation; watermarking; 0.13 micron; 3453 micron; 37.6 muW; 8 bit; ASIC; CMOS; VLSI implementation; chip area; chip power consumption; decryption; difference encoding; digital documents; encryption; fragile invisible watermarking; gray scale images; image processing; information embedding; online digital watermarking; spatial domain watermarking; Application specific integrated circuits; Authentication; CMOS technology; Cryptography; Discrete wavelet transforms; Frequency domain analysis; Image coding; Pulse modulation; Very large scale integration; Watermarking;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2003. Proceedings. 16th International Conference on

ISSN

1063-9667

Print_ISBN

0-7695-1868-0

Type

conf

DOI

10.1109/ICVD.2003.1183151

Filename

1183151