A methodology for accurate modeling of energy dissipation in array structures

There is an increasing need for obtaining a reasonably accurate estimate of energy dissipation in SoC designs. Array structures have a significant contribution to the total system level energy consumption. In this paper, we propose a new methodology to develop analytical models for accurately estimating energy dissipation in array structures. The methodology is based on the characterization of arrays for energy as a function of micro-architecture level inputs. The coefficients of the function are extracted using circuit level simulations. We apply the proposed methodology to develop energy models for three different array structures used in the Motorola e500 processor core. The models are validated by comparing them against post-layout SPICE simulation. The energy models are seen to be highly accurate with an error margin of less than 8%. While the experiments are specific to the e500 processor core based array structures, the methodology is generic and can be used to develop energy models for array structures of any SOC design.