DocumentCode :
3236532
Title :
Channel width test data compression under a limited number of test inputs and outputs
Author :
Ichihara, Hideyuki ; Kinoshita, Kozo ; Isodono, Koji ; Nishikawa, Shigeki
Author_Institution :
Fac. of Inf. Sci., Hiroshima City Univ., Japan
fYear :
2003
fDate :
4-8 Jan. 2003
Firstpage :
329
Lastpage :
334
Abstract :
A narrow channel width between a circuit under test and a tester increases the testing time. In this paper, we propose a channel width compression method when the channel width is limited. A given test sequence is partitioned into sub-sequences, whose widths can be compressed under the limited width. Each sub-sequence is compressed and expanded by a proposed dynamically re-configurable circuit located between the circuit under test and the tester. Since the hardware overhead depends on the number of partitions for a test sequence, a procedure to partition a given test sequence into a minimum number of sub-sequences under the channel width limitation is proposed. Experimental results show that our method can compress the width of a test sequence into a half through a quarter with a relatively small number of partitions.
Keywords :
VLSI; automatic testing; data compression; integrated circuit testing; channel width; channel width limitation; circuit under test; dynamically re-configurable circuit; hardware overhead; partitions; sub-sequences; test data compression; test inputs; test outputs; test sequence; testing time; Automatic testing; Built-in self-test; Circuit testing; Informatics; Integrated circuit testing; Pattern analysis; Pins; Test data compression; Test pattern generators; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2003. Proceedings. 16th International Conference on
ISSN :
1063-9667
Print_ISBN :
0-7695-1868-0
Type :
conf
DOI :
10.1109/ICVD.2003.1183158
Filename :
1183158
Link To Document :
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