Simultaneous switching noise projection for high-performance SOI chip design

Author

Wang, L.K. ; Chen, Howard H.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1996

fDate

30 Sep-3 Oct 1996

Firstpage

112

Lastpage

113

Abstract

This paper describes the circuit modeling techniques to predict on-chip simultaneous switching noise for high performance SOI circuits. The analysis includes both the inductive ΔI noise on the package level and the resistive I R drop on the chip level. By identifying the hot spots on the chip and ΔV across the chip, designers can optimize the placement of on-chip decoupling capacitors and effectively minimize the switching noise for SOI chips

Keywords

CMOS integrated circuits; circuit optimisation; integrated circuit design; integrated circuit modelling; integrated circuit noise; silicon-on-insulator; CMOS; chip level; circuit modeling techniques; high-performance SOI chip design; hot spots; inductive ΔI noise; on-chip decoupling capacitor placement; package level; resistive I R drop; simultaneous switching noise projection; switching noise minimization; CMOS technology; Capacitance; Chip scale packaging; Circuit noise; Circuit simulation; Delay estimation; Power supplies; Silicon on insulator technology; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1996. Proceedings., 1996 IEEE International

Conference_Location

Sanibel Island, FL

ISSN

1078-621X

Print_ISBN

0-7803-3315-2

Type

conf

DOI

10.1109/SOI.1996.552519

Filename

552519