A novel pattern transfer process for bonded SOI giga-bit DRAMs

Silicon-on-Insulator devices having a buried capacitor structure have been proposed by several authors as a 1 giga bit DRAM cell structure. However, several limits such as wafer cost, low throughput, and poor SOI thickness uniformity would prevent the practical application of this technology in spite of its distinct advantages such as shorter process step, easier backend process, and higher packing density. In this paper, we demonstrated the feasibility of a novel pattern transfer method combining the hydrogen implantation and selective polish stop process which can be applied to the fabrication of buried capacitor SOI structure with a low cost and high throughput