Title :
A method to estimate slew and delay in coupled digital circuits
Author :
Batterywala, Shabbir ; Shenoy, Narendra
Author_Institution :
Synopsys (India) Pvt. Ltd, Bangalore, India
Abstract :
Coupling capacitance has substantial impact on signal delays and arrival times. It is not always correct to de-couple them using the Miller factors of 0 or 2×. Towards this end, various de-coupling techniques have been studied in the literature. We extend them and suggest their use in static timing analysis. Our approach uses the switching factor based de-coupling approximation idea to compute the impact of coupling capacitors on signal slews and delays. We suggest an iterative table lookup scheme. The slew and delay tables for the library cell elements are looked up to compute slew and arrival times of signals in the presence of coupling capacitors. The method is easy to use with existing static timing analysis tools. It works with slew and delay tables, which are usually available with technology libraries. Other than table lookups, it requires minimal computation of two switching factors per coupling capacitor per iteration. Analysis and HSPICE simulation results are given to support the suggested method.
Keywords :
SPICE; capacitance; circuit simulation; coupled circuits; delay estimation; integrated circuit design; integrated circuit modelling; iterative methods; logic design; logic simulation; table lookup; timing; HSPICE; Miller factors; coupled digital circuits; coupling capacitance; coupling capacitors; decoupling approximation; iterative methods; iterative table lookup scheme; library cell elements; signal arrival times; signal delay estimation; slew estimation; static timing analysis; switching factor; Analytical models; Capacitance; Capacitors; Computational modeling; Coupling circuits; Delay estimation; Digital circuits; Libraries; Table lookup; Timing;
Conference_Titel :
VLSI Design, 2003. Proceedings. 16th International Conference on
Print_ISBN :
0-7695-1868-0
DOI :
10.1109/ICVD.2003.1183170