Title :
High-level synthesis of multi-process behavioral descriptions
Author :
Wang, Weidong ; Raghunathan, Anand ; Jha, Niraj K. ; Dey, Sujit
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
Abstract :
This paper presents a new high-level synthesis methodology to generate optimized implementations for multi-process behavioral descriptions. The concurrent communicating processes specification paradigm is widely used in digital circuit and system design, and is employed in all popular hardware description languages. It has been shown that inter-process communication and synchronization can result in complex timing inter-dependencies, which significantly affect the performance of a multi-process system. In this paper, we demonstrate that state-of-the-art high-level synthesis tools can generate significantly sub-optimal implementations for behaviors that contain concurrent communicating processes. We present an analysis of how inter-process communication impacts high-level synthesis steps, and describe a new methodology to adapt existing high-level synthesis tools to optimize multi-process descriptions.
Keywords :
circuit CAD; circuit optimisation; hardware description languages; high level synthesis; multiprocessing systems; resource allocation; synchronisation; complex timing inter-dependencies; concurrent communicating processes; digital circuit design; hardware description languages; high-level synthesis tools; inter-process communication; inter-process synchronization; multi-process behavioral descriptions; multi-process description optimization; multiple communicating processes; optimized implementations; resource allocation; Contracts; Digital circuits; Hardware design languages; High level synthesis; National electric code; Optimization methods; Partitioning algorithms; Performance analysis; Resource management; Timing;
Conference_Titel :
VLSI Design, 2003. Proceedings. 16th International Conference on
Print_ISBN :
0-7695-1868-0
DOI :
10.1109/ICVD.2003.1183178