Using Kohonen map for the placement of regular VLSI designs

The paper presents the formulation of a VLSI placement problem for regular designs (gate arrays) using a Kohonen self-organizing map. An abstract specification of the design is converted to a set of appropriate input vectors using a mathematical method, called “multidimensional scaling”. These vectors which have, in general, higher dimensionality, are fed to the self-organizing map at random in order to map them onto a 2-dimensional plane of the regular chip. The mapping is done in such a way that the cells with higher connectivity are placed close to each other, hence minimizing total connection length in the design. The results show improvement over other neural network based approaches in terms of both efficiency and the quality of results. The capability of our approach in handling external ports as well as nonrectangular (rectilinear) boundaries makes it appropriate for the placement of hierarchical designs