Title :
On single/dual-rail mixed PTL/static circuits in floating-body SOI and bulk CMOS: a comparative assessment
Author :
Cho, Geun Rae ; Chen, Tom
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado State Univ., Fort Collins, CO, USA
Abstract :
In this paper, single-rail and dual-rail mixed pass-transistor logic (PTL) and static CMOS circuits are presented. The circuits were synthesized using a genetic algorithm that determines the best mixture of PTL and static cells based on area and power. The mixed PTL/static circuits using the proposed method are compared with their static counterparts synthesized using a commercial logic synthesis tool in terms of area, delay and power in a 0.13 μm floating-body partially depleted silicon-on-insulator (SOI) and a 0.13 μm bulk CMOS technologies. Our experimental results on benchmark circuits from a commercial microprocessor indicates that the proposed mixed PTL/static circuits in both SOI and bulk CMOS technology outperforms their static counterparts in power consumption and/or performance.
Keywords :
CMOS logic circuits; VLSI; capacitance; circuit CAD; genetic algorithms; integrated circuit design; logic CAD; low-power electronics; silicon-on-insulator; 0.13 micron; Si; bulk CMOS technology; circuit synthesis; dual-rail circuits; floating-body SOI; genetic algorithm; logic synthesis tool; mixed PTL/static CMOS circuits; partially depleted SOI technology; pass-transistor logic; single-rail circuits; CMOS logic circuits; CMOS technology; Circuit synthesis; Delay; Energy consumption; Logic circuits; Logic functions; Silicon on insulator technology; Systems engineering and theory; Very large scale integration;
Conference_Titel :
VLSI Design, 2003. Proceedings. 16th International Conference on
Print_ISBN :
0-7695-1868-0
DOI :
10.1109/ICVD.2003.1183186
