Geometry scaling issues originated by extrinsic stress in SiGe HBTs

Author

Malladi, Ramana ; Slinkman, Jim A. ; Joseph, Alvin

Author_Institution

Microelectron. Div., IBM, Essex Junction, VT

fYear

2008

fDate

13-15 Oct. 2008

Firstpage

145

Lastpage

148

Abstract

The influence of stress induced by shallow trench isolation (STI) on the geometry scaling of DC parameters in SiGe HBTs is studied. It is shown that smaller devices experience higher stress effect due to the STI than larger devices. In the presence of stress, the scaling of transfer current with geometry can not be fully accounted by separating it into area and perimeter components. STI stress effect is studied here, by varying emitter-STI spacing and emitter geometry parameters. Stress is shown to affect current gain and BVCEO as well. Based on the Vbe shift for smaller geometries, stress seen by the device is estimated.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; geometry; heterojunction bipolar transistors; isolation technology; semiconductor materials; stress effects; SiGe; emitter geometry parameters; emitter-STI spacing; heterojunction bipolar transistors; shallow trench isolation; stress effect; Current density; Equations; FETs; Force measurement; Geometry; Germanium silicon alloys; Independent component analysis; Microelectronics; Silicon germanium; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 2008. BCTM 2008. IEEE

Conference_Location

Monteray, CA

ISSN

1088-9299

Print_ISBN

978-1-4244-2725-3

Electronic_ISBN

1088-9299

Type

conf

DOI

10.1109/BIPOL.2008.4662733

Filename

4662733