Title :
Simulating the impact of poly-CD wafer-level and die-level variation on circuit performance
Author :
Stine, Brian E. ; Boning, Duane S. ; Chung, James E. ; Ciplickas, Dennis ; Kibarian, John K.
Author_Institution :
MIT, Cambridge, MA, USA
Abstract :
In this paper, we present a methodology for simulating the impact of wafer-level (within-wafer) and die-level (within-die) variation on circuit performance. For a sample 0.25 μm 64×8 SRAM layout, the impact of both die-level and wafer-level poly-CD variation as measured through signal skew and delay is shown to be significant
Keywords :
MOS memory circuits; SPICE; SRAM chips; VLSI; circuit analysis computing; circuit layout CAD; delays; integrated circuit layout; 0.25 micron; SPICE; SRAM layout; VLSI; circuit performance; die-level variation; high-speed ICs; poly-CD wafer-level variation; signal delay; signal skew; Circuit optimization; Circuit simulation; Data mining; Delay; Etching; Integrated circuit interconnections; Lenses; Manufacturing; Optical imaging; SPICE;
Conference_Titel :
Statistical Metrology, 1997 2nd International Workshop on
Conference_Location :
Kyoto
Print_ISBN :
0-7803-3737-9
DOI :
10.1109/IWSTM.1997.629405
