A single-channel 10b 1GS/s ADC with 1-cycle latency using pipelined cascaded folding

Author

Razzaghi, Alireza ; Tam, Sai-Wang ; Kalkhoran, Pejman ; Wang, Yu ; Kuan, Chih-Yi ; Nissim, Brian ; Vu, Lan Duy ; Chang, M. C Frank

Author_Institution

High Speed Electron. Lab., UCLA, Los Angeles, CA

fYear

2008

fDate

13-15 Oct. 2008

Firstpage

265

Lastpage

268

Abstract

A 10b 1 GS/s ADC employing a single channel cascaded folding architecture is presented. Conversion speed of 1 GS/s is attained by incorporating low-power distributed track-and-hold amplifiers after each folder. This ADC achieves a record 55.6 dB peak SNDR and a 64 dB peak SFDR and sustains a latency of one clock cycle. DNL and INL at 1 GS/s sampling rate are measured 0.4 LSB and 1.1 LSB. Fabricated in a 0.35 mum BiCMOS process, the ADC consumes 2 W from a 3.5 V supply.

Keywords

analogue-digital conversion; cascade networks; distributed amplifiers; sample and hold circuits; 1-cycle latency; ADC; low-power distributed track-and-hold amplifiers; pipelined cascaded folding; power 2 W; size 0.35 micron; voltage 3.5 V; BiCMOS integrated circuits; Capacitors; Delay; Dynamic range; Frequency; Linearity; Quantum cascade lasers; Radar antennas; Radar tracking; Voltage; ADC; SiGe BiCMOS process; cascaded folding; folding; pipelined;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 2008. BCTM 2008. IEEE

Conference_Location

Monteray, CA

ISSN

1088-9299

Print_ISBN

978-1-4244-2725-3

Electronic_ISBN

1088-9299

Type

conf

DOI

10.1109/BIPOL.2008.4662758

Filename

4662758